With the increased complexity and density of today's high-end application-specific integrated circuit (ASIC) chips and higher-level electronic packages, there is a corresponding increase in the time required to verify the functionality of these complex package combinations. Typically, multiple independent logic built-in self-test (LBIST) runs are needed to verify the internal logic of multiple chips of an electronic package. If the electronic package has arrays, multiple array built-in self-test (ABIST) runs may also be executed as a separate step. In order to guarantee predictability for LBIST tests, the inputs to each chip are conventionally inhibited at the boundary logic. Subsequently, a second set of tests is performed to check input/output (I/O) connections at chip boundaries (e.g., reference IEEE Std 1149.1 Boundary Scan). These tests are typically DC-type tests, which verify that each I/O connection does not have a stuck fault, i.e., the I/O connection is not stuck at logic-level 0 or 1.
In order to perform the boundary scan tests, detailed information is required about the interconnections of each chip in the electronic package environment. For example, each I/O source, I/O sink, and I/O enable control path must be identified for boundary scan initialization and validation. Since the test topology set-up is typically remotely performed, with scan operations being transported to the hardware through a serial service processor interface such as JTAG, there is additional overhead introduced by performing these tests. Therefore, there exists a need in the art to further facilitate performing boundary scan checks, and there is a need to reduce the complexity of maintaining I/O connection information for multiple-chip electronic package configurations on a service processor. There is also a need to provide I/O boundary checking capability on less sophisticated hardware platforms that do not have service processor attachments.